We have so far studied combinational circuits . 到現(xiàn)在為止,我們已研究了組合電路。
A combinational circuit with only one output channel 一種只具有一個(gè)輸出通道的組合電路。
Delay analysis of combinational circuit in using programmable logic device 用可編程邏輯器件進(jìn)行組合電路設(shè)計(jì)時(shí)的延時(shí)分析
This paper discusses equivalence checking for combinational circuits and analyzes the key techniques of fan algorithm 摘要討論了組合電路的等價(jià)性檢驗(yàn)方法,分析了fan算法的關(guān)鍵技術(shù)。
We check equivalence of combinational circuits with fun algorithm , and experimental results show that fan algorithm is efficient 利用該算法進(jìn)行了組合電路的等價(jià)性檢驗(yàn),實(shí)驗(yàn)結(jié)果表明了該方法的有效性。
Compared with the method only using universal cut or special cut , the method can obviously improve the speed of verification for combinational circuits 與只基于通用割集或?qū)S酶罴尿?yàn)證方法相比,該方法可以使組合電路的驗(yàn)證速度明顯提高。
To increase the speed of equivalence checking for combinational circuits , a new method using internal equivalence information of circuits in verification was proposed 摘要為了提高組合電路的等價(jià)性驗(yàn)證速度,提出了一種利用電路內(nèi)部等價(jià)信息的新型驗(yàn)證方法。
The method of optimization is classified into two categories : ( 1 ) combinational optimization method , which is the optimizational method of combinational circuit is directly used for the sequence circuit 優(yōu)化的方法大致可分為兩類: ( 1 )組合優(yōu)化方法,即將組合電路的優(yōu)化方法直接用于時(shí)序電路。
Based on rtl circuits structure described in etbl , this dissertation presents two hierarchical atpg algorithms based on structure for rtl combinational circuits . the two algorithms generate tests for rtl circuits by test sets for modules 本文在etbl描述的rtl電路結(jié)構(gòu)的基礎(chǔ)上,進(jìn)行rtl組合電路自動(dòng)測(cè)試產(chǎn)生算法的研究,提出了兩個(gè)基于結(jié)構(gòu)的rtl組合電路分層測(cè)試產(chǎn)生算法。
Power sensitivity is defined and some related mathematical models are deduced , which bring on a set of theoretic power sensitivity analysis methods for combinational circuits . experimental results verify that the method can be used for dynamic power and leakage power 另外文章還提出了一種靜態(tài)功耗壓縮估計(jì)方法和一種雙閾值電壓快速優(yōu)化方法,它可以很好地用在低漏電電路的設(shè)計(jì)中。